The present invention pertains to an improved precomputation logic and method for minimizing power dissipation of integrated circuits.
Integrated circuit (IC) semiconductor chips are found in virtually every conceivable electronic device ranging from consumer products to office equipment, telecommunications gear, all sorts of instrumentation, etc. With rapid advances in semiconductor technology, ever increasing numbers of transistors can be fitted onto a single IC chip. Logic density has reached the point where a single IC chip today is capable of containing upwards of millions of transistors. Indeed, the processing power and versatility of these IC chips keep increasing while manufacturing costs keep decreasing. These trends coupled with constant improvements in miniaturization, have made it feasible and practical to develop highly sophisticated portable electronic products. Portable products, such as laptop computers, cellular telephones, etc. are in great demand by today""s highly mobile professionals. Other battery operated electronic devices include radios, televisions, electronic games, calculators, tape recorders, CD players, pagers, and even satellites.
The major problem that all of these battery operated devices face is the inevitable fact that they must eventually shut down when their batteries expire. In an effort to extend the operating time of these portable devices, designers have resorted to incorporating additional batteries, utilizing exotic batteries having greater capacities, and reducing the number of IC chips. Each of these solutions has its disadvantages. Additional batteries make the portable devices heavier, bulkier, more cumbersome. Exotic batteries are prohibitively expensive. And reducing the amount of chips limits the device""s functionality and versatility.
One solution which does not have these attendant disadvantages relates to xe2x80x9cprecomputation.xe2x80x9d Precomputation refers to the art of incorporating specialized additional circuits which attempt to forecast or anticipate the output logic values of a more complex, standard circuit. By analyzing the functions of the standard circuit, it may be possible to predict the circuit""s output values with 100% accuracy under certain sets of input conditions. The precomputation circuit detects these input conditions and generates the output values ahead of time. It is these precomputed output values which are subsequently used. The goal is to recognize and exploit the existence of simpler precomputation functions. In those instances whereby output logic values can be precomputed, the more complex, standard circuit need not generate its standard output values and, hence, can be disabled. Because the precomputation circuit is smaller and simpler than that of the standard circuit, it consumes less power. Thus, a significant amount of power can be conserved by running the simpler precomputation circuit while shutting down the more complex and power-draining standard circuit. For some circuits, it is possible to achieve 75% reductions in average power dissipation by using precomputation. Another benefit conferred by precomputation is that, by reducing power dissipation, it also helps reduce the heat generated by an IC chip. Heat buildup limits the speed at which an IC chip can run and can shorten its life span. Hence, precomputation is very beneficial.
There exist many different architectures for implementing the precomputation circuit. An article by Mazhar Alidina, Jose Monteiro, Srinivas Devadas, Precomputation-Based sequential Logic Optimization for Low Power, IEEE Transactions on Very Large Scale Integration Systems, Vol. 2, No. 4, December 1994, describes several precomputation architectures. As an example, FIG. 1 shows a typical prior art precomputation architecture. Register 101 is used to load the x1-xn input values to standard circuit 102. If precomputation is not possible, then the output value on line 103 from standard circuit 102 is fed via OR gate 104 and AND gate 105 to register 106 corresponding to a subsequent pipeline section. In this case, precomputation does not offer any savings in the power dissipation. On the contrary, the additional precomputation circuitry 107-111 actually causes power dissipation to increase. However, if x1 and x2 are such that precomputation is successful, then NOR gate 109 sends a load enable (LE) signal to disable register 101. This prevents any transitions being input to standard circuit 102. Consequently, standard circuit 102 does not dissipate any power. The g1 block 107 represents the case where an output value of xe2x80x9c1xe2x80x9d is precomputed. Flip-flop 110 latches this value and forces OR gate 104 to also output a xe2x80x9c1.xe2x80x9d Thereby, a value of xe2x80x9c1xe2x80x9d is driven as an input to register 106, regardless and independent of whatever the output is from standard circuit 102 since it is assumed that gl and g2 can never be xe2x80x9c1xe2x80x9d at the same time. Similarly, the g2 block 108 represents the case where an output value of xe2x80x9c0xe2x80x9d is precomputed. Flip-flop 111 latches this value and forces AND gate 105 to drive a xe2x80x9c0xe2x80x9d as an input to register 106, regardless and independent of whatever the output is from standard circuit 102. In these cases, power dissipation is minimized because standard circuit 102 is effectively shut down. Other prior art precomputation architectures are depicted in FIGS. 2 and 3.
Although these prior art precomputation architectures help reduce power dissipation, it would be preferable if there were some better way to achieve even greater power conservation. The present invention offers an improved precomputation architecture and method which results in less power dissipation, takes less circuitry to implement, and has less time delay.
The present invention pertains to a novel precomputation architecture and process for use in IC chips, which grants improved reductions in power dissipation, requires less logic to implement, and relaxes critical timing constraints. The functions performed by an original, standard circuit is replaced by two or more mutually exclusive circuits xe2x80x9cAxe2x80x9d and xe2x80x9cB.xe2x80x9d Circuit xe2x80x9cAxe2x80x9d is used to calculate output values if precomputation cannot be performed. However, if the output values can be precomputed, the precomputation circuit xe2x80x9cBxe2x80x9d is used to calculate the output values. Precomputation circuit xe2x80x9cBxe2x80x9d is smaller, simpler, and consumes less power than precomputation circuit xe2x80x9cAxe2x80x9d. Hence, whenever the appropriate set of input signals are in a condition such that precomputation can be performed, power is conserved by using the simpler circuit xe2x80x9cBxe2x80x9d rather than the more complex circuit xe2x80x9cAxe2x80x9d to calculate the final output values. An extremely small and simple decision circuit is used to determine whether precomputation is possible. Depending on whether precomputation can be performed, either circuit xe2x80x9cAxe2x80x9d or circuit xe2x80x9cBxe2x80x9d is activated. They are never both activated at the same time. Only one or the other circuit is active while the unused circuit is disabled in order to conserve power. The decision circuit directs a multiplexer to select the appropriate output values generated by either circuit xe2x80x9cAxe2x80x9d or xe2x80x9cBxe2x80x9d as the case may be.
In the present invention, the decision circuit merely selects either circuit xe2x80x9cAxe2x80x9d or xe2x80x9cBxe2x80x9d based on its determination of whether precomputation is possible. It renders its selection at a previous cycle. The actual computation of the output values is made by either circuit xe2x80x9cAxe2x80x9d or circuit xe2x80x9cBxe2x80x9d in a subsequent cycle(s). In contrast, prior art precomputation circuits determine whether precomputation is feasible and also calculate the final output values. In the prior art, both of these functions are performed in the previous cycle. However, the present inventors have discovered that one only needs to determine whether precomputation is possible in the previous cycle. The actual computation of the final output values can be postponed until a subsequent cycle. This novel concept offers several advantages. Namely, with the present invention, only the decision circuit is continuously kept activated. This is in direct contrast to the prior art, whereby the entire precomputation circuitry is continuously kept active. Since the decision circuit performs the single function of precomputation detection, it draws less power than prior art precomputation functions which perform both functions of precomputation detection and output value generation. Furthermore, postponing the actual computation of the output values until subsequent cycle relaxes critical timing constraints. In addition, less transistor logic is required to implement the decision circuit as opposed to traditional precomputation circuits.